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Instruction and Data Address Tracing Technique for POWERPC Machines Disclosure Number: IPCOM000013287D
Original Publication Date: 1999-Oct-01
Included in the Prior Art Database: 2003-Jun-18

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Disclosed here is a new technique using a combination of the POWERPC* trace and performance monitor features to efficiently produce instruction and data traces. Providing instruction and address traces is a very important part of system tuning and future system design. There are many different methodologies for providing this support, each of which having its benefits and problems. Software instruction and data address tracing tools usually either instrument the code to be traced or use the tracing facility of the machine to single-step though the code and decode all the instructions at each step looking for load or store instructions. When using the instrumentation technique, one has to first discover the basic blocks of the code to be traced which is a non trivial and usually slow operation especially on machines with dynamic branches like all the POWERPC based machines. When using the tracing facility of the processor, tracing becomes extremely slow because of the necessary instruction decoding after each instruction. In both cases, the data address must be calculated from the decoding of the instruction interrupted, further slowing down the trace. The technique disclosed here uses a combination of four POWERPC features to efficiently produce instruction and data address traces :