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Efficient emulation of byte-serial operation semantics on a long-instruction word architecture Disclosure Number: IPCOM000013360D
Original Publication Date: 2000-Mar-01
Included in the Prior Art Database: 2003-Jun-18

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Byte serial semantics are required for the correct implementation of storage-to-storage oper- ations in System/390. This poses several problems in the execution using binary translation to a register-oriented architecture since a high-performance implementation will use "widening to perform operations not at the byte level, but at the machine word level. The present disclosure describes a hybrid hardware/software solution to ensure serial semantics while allowing widening to be used for efficiency. The present invention is to be used in con- junction with an architecture for data speculation which allows to mark registers with an exception bit, as used in IBM Research's DAISY architecture or the Intel 1A-64 architecture. A difference between byte-serial and word-based processing can only be observed in the case of overlapping source and target operands. Thus, widening can still be used beneficially in the majority of cases, and special care must be taken to detect overlap of operands which need special processing. Since storage-to storage operations are two-operand, instructions, the target address is also present as one source operand. Thus, to detect overlap between the source and target address of a storage-to-storage operation, it is sufficient to detect overlap between the two source addresses.