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L2 Cache Data Capture Clock Window Margin Circuit

IP.com Disclosure Number: IPCOM000013395D
Original Publication Date: 2000-Jun-01
Included in the Prior Art Database: 2003-Jun-18

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This circuit is used to determine the window of margin for the L2 Data capture clock while the processor is running and without impacting the current program. The previous designs did not have this, and determining these parameters would take several hours, required custom programs and the machine needed to be power cycled or IPL'd after each data point. With this circuit the processor does not need to be executing a special program and can be done with any program that uses the L2 cache. The processor does not need to be power cycled or IPL'd after each window margin evaluation cycle and takes only seconds to complete. The previous method was only done on a select few machines where as with this circuit it could be done on every machine and could be used throughout the life of the processor to evaluate the margin of the L2 capture clock. The capture clocks for the L2 data are programmable by the service processor in the existing design. These programmable clocks have a range that exceeds the functional operating range. This circuit duplicates the programmable clock delays and part of the data path. There are separate circuits for determining the minimum and maximum extremes of the clock. These circuits operate simultaneously and independently to determine the clock extremes. Using these duplicate clock circuits and a sample data bit, the clocks are adjusted until a miscompare occurs between the normal data path and each window margin data path. The results of the clock settings are saved in registers which can be read by the service processor. The process of initializing the clock settings and cycling through the routine can be repeated as desired without impacting the normal L2 data flow. 1