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Lightweight Run-Time Conditional Switches on IA64 Disclosure Number: IPCOM000013403D
Original Publication Date: 2000-Oct-01
Included in the Prior Art Database: 2003-Jun-18

Publishing Venue



Disclosed is a method for managing conditional paths in performance critical code on the IA64* architecture. The disclosure specifically addresses the need in an operating system kernel to have highly optimized code paths yet allow for flexibility as key features of the operating system are enabled or disabled. The method employs existing technologies provided in the IA64 architecture including special purpose kernel registers and predication. In software in general, especially operating systems and performance critical code, it is desirable to streamline code paths as much as possible by avoiding compare and branch sequences in performance critical code. In an operating system, especially one where a single binary image of the operating system supports all possible platforms, modes, and settings, it becomes difficult to streamline this code and at the same time conditionally support all of the various features. The invention is specific to software running on the IA64 architecture, and is described in the context of how it was implemented which was for kernel level conditional switches. A kernel flag word is maintained that contains a bit for any run-time decision that might need to be made in performance critical (state management, system call, etc.) code. An example of these bits are for Performance Tracing Enable/Disable, System Trace Enable/Disable, Lowlevel Kernel Tracing Enable/Disable, System Call Tracing Enable/Disable, C2 security or better enabled/disabled, etc. Each of these conditionals result in a different path, or additional code being executed in performance critical paths. Instead of having to test each of these conditions independently, which could result in multiple separate compare instructions with associated conditional branches, the performance critical code paths load the current value of kernel flags into the IA64 predicate register. Then in that one instruction, all possible conditional results are set in their assigned predicate. Since the kernel flag word is kept in a special register, there aren't even any memory references associated with determining the results of each condition. The performance critical code then contains predicated instructions that branch out-of-line to accomplish the task. If the flag isn't enabled, the corresponding predicate will be FALSE, and the predicated instruction in the mainline path essentially ignored with no performance impact of introducing compares and branches to the normal path. Trademark of the Intel Corp.