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The 630+ Processor Enhanced Implementation of LBIST Diagnostic Logic Disclosure Number: IPCOM000013451D
Original Publication Date: 1999-Nov-01
Included in the Prior Art Database: 2003-Jun-18

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Talal Jaber


This invention describes the implementation of the 630+ Processor Logic Built_in Self_Test(LBIST) diagnostic logic. This logic implementation is capable of detecting and isolating the first fail during LBIST tests and can identify the failing scannable latch(es) within any of the LBIST scan channels. Historically, LBIST tests were implemented as `GO/NOGO' tests. The addition of the LBIST diagnostic logic on the 630+ processor introduced a new debug capability in fault detection and isolation. This invention makes use of the STUMPS architecture for a LBIST implementation on the 630+ processor. It also relies on a on-chip LBIST controller to provide control of the chip STUMPS configuration, scan and functional clock generation, initial loading of the LBIST PRPG and MISR as well as other registers and the final scan out operation of the LBIST scan channels and the LBIST PRPG, MISR and other LBIST control registers. The on-chip LBIST controller is JTAG based and can receive instructions over the JTAG testability bus to control LBIST as well as other test and debug operations. The on-chip LBIST controller is called COP `Common On-chip Processor' and has been disclosed in previous publications in the IBM Journal Of Research And Development, Volume 34, Number 1, January 1990. The novelty of this invention is in the introduction of three additional elements to the control logic of LBIST. These three elements are described below: