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State-of-the-art Wire Bond Package Disclosure Number: IPCOM000013529D
Original Publication Date: 2000-Oct-01
Included in the Prior Art Database: 2003-Jun-18

Publishing Venue



In this design the use of DPS (Develop-Plate-Strip) plating process is employed to produce a 30 metal copper die bond pad on laminate chip carrier. Another important feature of this package design is the use of a polyimide top surface on the active circuitry of the wire bond die. Here we are proposing the use of polyimide on the active side of the die. To meet aggressive Soft Error Rate (SER) requirements, it is important to use a low alpha particle overmold or glob top material. Two solutions are Hysol 4450 a registered trademark of Dexter Hysol Corp.) (glob top) and a new version of Toshiba KE 2100A (a registered trademark of Toshiba Corp.). Also, recent HAST testing has shown that the ASM soldermask is capable of withstanding 192 hrs. of HAST testing. The figure below schematically shows these features in a wire bond laminate module. Features of this Design: 1. A low alpha particle overmold with less than or equal to 0.001 counts/cm2/hr. 2. The use of a thin polyimide layer on the active surface of the die, which will act as a shield for any spurious alpha particles that may remain in the package.