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HSTL clock integrity monitor Disclosure Number: IPCOM000013559D
Original Publication Date: 2000-Aug-01
Included in the Prior Art Database: 2003-Jun-18

Publishing Venue



HSTL clock integrity monitor The problem to fix is, in a system generating HSTL clocks for a slave part, how to monitor the integrity of these clocks. As described on figure 1, a clock is generated by the VCXO. A clock buffer gives more power to feed several adapters, let’s take one module. It is used to feed an adapter and it’s internal logic. The adapter send back the clock (feed back clock),and is connected to the Up input of the integrity monitor.An other module of the clock buffer is connected to tha Down input of the integrity monitor.The positive, negative and equal zero output of the integrity monitor is connected to readeable I/O of a microcontroller of the reference card. CLOCK BUFFER