Browse Prior Art Database

SEAL algorithm implemented in hardware Disclosure Number: IPCOM000013564D
Original Publication Date: 2001-Apr-01
Included in the Prior Art Database: 2003-Jun-18

Publishing Venue



Disclosed here is a method for hardware implementation of SEAL cryptography algorithm. Table 1 shows original SEAL algorithm[1][2]. Array T use SRAM memory and it's address can be generated one clock before. WP and a,b,c,d update operations can run parallel to final round operations. Table 2 shows modified equations suitable for hardware implementation. In Figure 1, we give an example of data-path circuit of SEAL hardware engine. Peek performance of this hardware is: 256 32 [bit] Rate[Mbit/sec] Freq[MHz] (12 9*64)