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Test and Diagnosis of Global System Clock Distribution Network Defects in a Scan-based VLSI Design

IP.com Disclosure Number: IPCOM000013604D
Original Publication Date: 2000-Nov-18
Included in the Prior Art Database: 2003-Jun-18

Publishing Venue

IBM

Abstract

This invention disclosure addresses the problem of effectively testing these system clock distribution networks or trees and pinpointing logical fault locations within these networks. Specifically, the problem addressed is that of system clock distribution test and diagnosis in scan based designs supported by a structural test methodology. These type of problems are usually encountered early in the technology's life cycle and their diagnosability is critical in improving the process so it quickly achieves manufacturing yield levels. An inability to improve the technology and yield of the device can greatly impact a program or at least severely minimize the revenue that could be realized. Rapid diagnosis to a location for Physical Failure Analysis (PFA) is needed for understanding and improving the process. Since these clock distribution networks span the entire chip utilizing multiple levels of metals, it is important to develop a technique to locate any manufacturing defects caused by marginal design practices in a quick and efficient way. Figures and Drawings