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Method to synchronously stop all clocks in a system and re-start Disclosure Number: IPCOM000013667D
Original Publication Date: 2001-Jan-01
Included in the Prior Art Database: 2003-Jun-18

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Stopping the clocks in a large computing system upon the detection of a hard checkstop condition or a debug trigger can be accomplished synchronously. In previous systems, the chip-to-chip propogation delay for the checkstop signal was greater than the chip's cycle time, causing the stop to be asynchronous to the chip clock. A simple method to make the stop synchronous is to define a synchronous IO interface for the stop signal such that the launch to capture time is longer than the propogation delay. In a system with a very high speed clock, the width of the launch to capture timing in terms of processor clocks must be made large for the synchronous stop signal. One implementation scheme is to make use of the counter that generates the bus clock ratios of 1:1, 2:1, 3:1, 4:1, 6:1, 8:1, up to and including 12:1. This counter rolls over after it reaches 47 because all of the bus ratios may divide into 48 without a remainder. This is to allows for the bus transfer of the stop signal to be based upon a 48 processor clock wide bus timing. A synchronizing operation must be performed once to allign this counter between all the chips in the system to ensure that all the chips are communicating with the full allotment of "N" processor clocks for an N:1 bus. Once the synchronized 0 to 47 bus ratio counter is available in the system, a 48:1 bus ratio can be readily supported for the synchronous stop signal. The chip initiating a checkstop would launch at the beginning of the 48:1 bus cycle, and all of other chips in the system would receive the checkstop signal prior to at the beginning of the next 48:1 bus cycle. The receiving chips would capture and evaluate the stop signal at the 48:1 bus cycle time. For debug proposes, the beginning of the 48:1 bus cycle may be made programmable with respect to the value in the 0 to 47 counter.