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IP.com Disclosure Number: IPCOM000013697D
Original Publication Date: 2000-Aug-01
Included in the Prior Art Database: 2003-Jun-18

Publishing Venue



The problem of random access times to SDRAM can be improved by storing data across the internal banks of larger SDRAM memories. By storing the data starting with the first row of bank 0 then the first row in bank 1 to the first row of bank n, then to the second row in bank 0 and so on through the last row in the last bank, see Figure 1. By spacing the banks in this manner, the SDRAM banks are set up to increase the chance that the next access is in a different bank. This is different from the previous method where data was stored from top to bottom, see Figure 2. In that case, it was more likely that data was going to be in the same bank, but a different row (row miss). When a row miss occurred, the bank had to be precharged and then reopened, this not only caused a bank open delay but added the precharge delay. The striping of data will allow for the next bank to be opened while the data from the previous operation is going on. Being able to open the next bank and row while data is being transferred will allow for a greater chance of as close as possible to seamless data transfers, see Figure 3. By opening the next bank and then being ready to interrupt the current data transfer with the new one when the desired data has come to an end, the data bus could then be used to its maximum potential. Dead time on the bus would not be eliminated, but it could be minimized. The data striping will be implemented by taking the full data address and removing the lower bits for the column address. Then the next lower bits for the bank select bits. The next bits will make up the row address. Any other address bits could be used as chip selects for other external banks of SDRAM chips. (hardcopy figure 1)