SRAM Leakage Current Reduction Method
Original Publication Date: 2000-Dec-01
Included in the Prior Art Database: 2003-Jun-18
The following disclosure describes a circuit configuration for reducing standby-leakage current in SRAMs and other various circuit configurations. With the advent of higher levels of circuit integration, the issue of standby power is fast becoming a problem. This is especially important for battery driven applications and applications that spend most of their time in a sampling or inactive mode. In most applications, SRAMs are also being employed and the percentage of SRAM circuitry relative to the overall design is ever increasing. To combat leakage current, often times the channel lengths of the pass transistors are increased to raise the threshold voltage of the devices. The increased channel length reduces the short-channel leakage effects and thus the leakage current of the nfet pass gates. While this is an acceptable approach the magnitude of improvement is on the order of 25%. What is needed is a more dramatic reduction in leakage current without sacrificing performance. The approach that we will disclose in the following pages will reduce the overall leakage current associated with the pass transistor by 6x for a typical SRAM configuration with 32KBytes . The basic concept is to dynamically bias the Word Lines of the SRAM to a negative potential when the SRAM is deactivated or in sleep mode. The word line driver or word line buffer has voltage swings of ground and vdd. When a word line is selected, the word line driver buffer is activated to Vdd. When inactive, the word line is set to ground. The concept here is to detect sleep mode, and lower the word line driver’s or buffer’s output potential to a value below ground enough to reduce the leakage path conductance while not forward biasing the source/drain to bulk diode. Figure 1 illustrates a basic SRAM cell. The bit lines are pre-charged to Vdd, the word line, which is driven by the word line driver, is at ground potential when the cell is deactivated. The contents of the cell could be either a "0" or a "1", but for the purposes of this illustration, node A is set at "0". There are 3-potential leakage paths; the path from the true bit line through the nfet pass gate (device N1) to ground through the nfet in inverter #2; the leakage associated with the nfet in inverter #1 from the active pfet of inverter #1; and the leakage associated with the pfet in inverter #2 through the active nfet in inverter #2. In this article we will focus on the leakage associated with the nfet pass gates.