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Bit Line Charge Up Circuit for Loadless Four-Transistor SRAM

IP.com Disclosure Number: IPCOM000013763D
Original Publication Date: 2002-Apr-11
Included in the Prior Art Database: 2003-Jun-18

Publishing Venue

IBM

Abstract

Bit-Line Charge Up Circuit for Loadless Four-Transistor SRAM. This paper describes circuit technique which reduces influence of coupling noise of adjacent bit-lines in loadless four transistor SRAM array. This circuit tequnique uses cross coupled pfet devices on a bit-line pair to recover voltage drop which occurred during a read access cycle. These added device size is small, and any additional control signal is not required. This technique is suitable for the loadless four transistor SRAM array using a direct sensing scheme or no sense amplifier scheme. The loadless four-transistor SRAM cell does not have load devices which six-transistor SRAM cell usually has. The stored high voltage(=vdd voltage) in the four-transistor SRAM cell is kept by leak current which comes from bit-line through an access transistor. Therefore when the cell is accessed, this high level node is affected by coupling noise of adjacent bit-lines, and the voltage of the node is dropped from vdd voltage if there is no restoring devices on the bit-lines. This voltage drop becomes a cause of miss-read operation or having a retention time. Because the high voltage in a cell is kept by very small leak current only. Therefore this leak current can not recover the voltage drop within a cycle time. Some schemes are known for reducing or improving the voltage drop. #1. use of twisted bit-line layout. #2. activating pre-charge devices during the read cycle, too. #3. use of a sense amplifier for restoring cell.