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Data integrity on parity-less buses Disclosure Number: IPCOM000013773D
Original Publication Date: 2001-Mar-01
Included in the Prior Art Database: 2003-Jun-18

Publishing Venue



A number of processors do not implement parity on data buses. This can lead to errors in operation or corruption of data as errors during data transfer cannot be spotted by the receiving device. This invention describes a method to solve this problem for cases where the processor has a data bus wider than the width of the data to be transferred (this is often the case where the processor implements a general-purpose peripheral bus to which many types of peripheral devices are attached). The advantages of the invention are a resulting error detection capability better than simple parity protection, and a low cost of implementation in terms of processor computation and receiver logic. Consider the case where a processor implements a data bus n bytes wide, but without parity protection. The processor needs to communicate with a peripheral device on the bus where the data width to be transferred can be less than the bus width. In a simple example, the required data width is n/2 bytes. If the processor was to duplicate each byte during a write to transmit n bytes (2 sets of the n/2 required data bytes) then the receiving device could check that the byte-pairs matched before considering the write as valid, and writing away the data. In a similar manner, on a read by the processor the peripheral device could send out a duplicate data segment which could be checked by firmware on receipt. Specifically, the advantages are as follows: Byte duplication or comparison is far cheaper than bitwise XOR-ing in terms of processor cycles; thus the scheme provides data integrity without a large computational overhead at the processor. Byte duplication and byte-to-byte comparison is also cheaper (in terms of logic resources used) than bitwise XOR-ing in general-purpose logic devices such as Complex Programmable Logic Devices (CPLDs) which are often used to implement "glue logic" on a processor bus. The CPLD may use the received data directly, or be used to generate a more conventional data protection scheme for forwarding to other devices. Whereas a simple parity scheme will detect any error involving an odd number of invalid bits, the scheme outlined here will detect any error except where the same bit in each paired word is similarly corrupted. It will therefore detect any error involving an odd number of bits (as a simple parity scheme), and also an error involving an even number of bits as long as the error is not exactly duplicated in both bytes. By inspection, this is a better probability of error detection. The scheme can also detect which bits of the transmitted word are in doubt, as opposed to just the fact that there is an error. 1