Browse Prior Art Database

Bit switch in semiconductor memory

IP.com Disclosure Number: IPCOM000013777D
Original Publication Date: 2000-Jul-01
Included in the Prior Art Database: 2003-Jun-18

Publishing Venue

IBM

Abstract

Bit switch in semiconductor memory Disclosed is a circuit of bit switch in semiconductor memory for reducing rush current and power consumption by using read and write control signals. Reduced rush current leads to a stable operation of peripheral components and itself. A semiconductor memory has bit switches to read data from and write data to memory cells. A bit line connects to plural memory cells. The bit switches locate between data lines and bit lines. They connect required number of bit lines to data lines. In read and write operation of a dynamic random access memory (DRAM) and a static random access memory (SRAM), the bit switch usually connects one bit line to one data line. In search operation of a content addressable memory (CAM), it usually connects plural bit lines to one data line. Figure 1 shows a circuit schematic including a conventional bit switch. The bit switch (TN2/TN3) and a pre-charging device (TN0/TN1) use only N-MOSFETs (NFETs) because the logic high voltage level of a bit line (BLT/BLC) and a data line (DLT/DLC) is limited to Vdd Vtn, where Vdd means power supply voltage and Vtn means threshold voltage of NFET, in order to reduce current consumption. The bit switch connects the bit line to the data line in read, write and search operation. The pre-charging device pulls the bit line up to Vdd Vtn. The P-MOSFET (PFET), TP0, equalizes BLT and BLC. A data line pre-charge circuit not shown here pre-charges DLT and DLC up to Vdd Vtn. BLPCEQBSN controls the bit switch devices. When it is high, the pre-charging device pre-charges the bit line up to Vdd Vtn and a inverter, I0, forces EQNBS low. The bit switch is off to isolate the bit line and the data line. When BLPCEQBSN goes low, EQNBS goes high and the bit switch turns on to connect the bit line and the data line.