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Methods to isolate and control processor to memory transfers using indirect software procedures. Disclosure Number: IPCOM000013798D
Original Publication Date: 2000-Jan-01
Included in the Prior Art Database: 2003-Jun-18

Publishing Venue



This invention provides the ability to create and control specific data transfers between the processor subsystem and the memory subsystem of a computer. The intent is to create data traffic between the subsystems such that the transfer cycle type and the frequency of cycles (data throughput or load) is strictly controlled. The ability to write/read cache lines between one or more processors' cache subsystem and the memory subsystem was needed in an operating system like NT that prohibits direct control of caches because of the operating systems use of virtual memory