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SECOND GAIN STAGE (SGS) WITH ENABLE, POLARITY REVERSAL, AND POWER DOWN FEATURES

IP.com Disclosure Number: IPCOM000013804D
Original Publication Date: 2002-May-01
Included in the Prior Art Database: 2003-Jun-18

Publishing Venue

IBM

Abstract

Second Gain Stage (SGS) with Enable, Polarity Reversal, and Power Down Features The output stage of the Analog Front End (AFE) module designed for the Liner Tape Open (LTO) needed the capability of being tri-stated in order to be able to dot-and the outputs of more than one AFE, needed the capability to reverse the phase of the output signal, and needed to have power down capability in order to conserve power. These requirements have been achieved by one set of circuit elements reducing cost and complexity. The circuit functions as follows. Three control signals, CHIP_SELECT, PD (power down), and NEGOUT (invert the output signal), are inputs to the circuit. A block of logic produces five output control signals, A, B, BBAR, C and CBAR. BBAR and CBAR are the logical NOT of B and C. These output control signals are related to the inputs by the following logic relations: A NOT(CHIP_SELECT) OR PD B NOT(CHIP_SELECT) OR PD OR NEGOUT BBAR NOT(B) C NOT(CHIP_SELECT) OR PD OR NOT(NEGOUT) CBAR NOT(C)