Browse Prior Art Database

BLOCK PCI ARBITRATION ON DELAYED READ REQUESTS

IP.com Disclosure Number: IPCOM000013819D
Original Publication Date: 1999-Dec-01
Included in the Prior Art Database: 2003-Jun-18

Publishing Venue

IBM

Related People

Authors:
EQ GARCIA JA YANES CE JONES GW BATCHELOR RL ELLISON R MEDLIN B TAFESSE

Abstract

On a PCI bus containing a PCI bridge and multiple PCI agents, a method is described to prevent the agents from thrashing the PCI bus when they perform delayed reads through the bridge or when the bridge has no room for the agents' write data. The method uses an arbiter, to determine the internal state of the PCI to PCI bridge, and minimize retries on read operations, where little or no data is available in the bridge's read return buffers. The arbiter also ensures that adequate write buffering is available for write operations. The net effect of these techniques is to increase the data per bus transaction ratio, thus increasing total bus throughput. The secondary PCI bus arbiter is located in the PCI bridge. While meeting the requirements for the PCI specification, the arbiter takes advantage of knowledge about the internal workings of the bridge. The arbiter is a two tiered arbiter. The first tier has the highest priority and arbitrates among agents which either 1) do not have a delayed read operation in progress; or