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Method of shifting memory element data patterns with varying data types and variable addressing to detect invalid data coupling between memory elements. Disclosure Number: IPCOM000013820D
Original Publication Date: 2000-Jan-01
Included in the Prior Art Database: 2003-Jun-18

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ABSTRACT: A very flexible method was needed to find memory problems and cause specific memory operations within an integrated memory element in a computer by simply shifting bits within a memory element slightly differently relative to other memory elements. Within a computer system there are many places where undesireable interaction can occur between two memory elements due to physical proximity(i.e data line cross talk) or within time(i.e. one processor/memory bus tranfer latches data from the previous transfer). If this corruption occurs within the data phase of a transaction a program could store or read invalid data. If the data is used as control then this can cause the program to generate an invalid branch which sometimes can bring the operating system environment down. By including the type of methods described a tool designed to validate memory integration of hardware, operating system becomes more effective at finding problems relating to any memory element within this integration. This includes the physical memory, busses, registers and any other physical manifestation of a memory element. The idea is to write a memory location with a data pattern and shift the bits via an arithmetic shift left or right and write that pattern to the next memory location. This will repeat until you reach the boundary condition where 1 is at the left or right(depending on ASR or ASL operations, respectively). The next address written continues this bit shift and is initialized the same as the previous operation. A simple case is setting all bits within a data type like DWord to 1 and all other bits set to 0. This is called a walking 1 pattern. Alternately, the walking 0 pattern keeps all bits set to 1 except for one. The following is a walking ones pattern for DWords that illustrates the bit shifting left. 0x20000000 0x40000000 0x80000000 0x00000001 0x00000002 0x00000004 0x00000008 The flexibility that was needed involved several different mechanisms. All of these in combination allow a wide variety of permutations and randomness to improve the probability that a specific hardware or software problem of this type can be detected. First, this method must be able to go from the bottom of a memory buffer up or vice versa. This directional change sometimes results in different rates due to architectural implementation for instance in the hardware speculative cache fetching. Second, various data types must be available. The variation of the data types causes different software/hardware operations which can bring out timing problems. For instance, doing a byte write will cause read/modify write cycles on the processor/memory bus that is different than doing a word type write. Third, the direction that the bit moves within the memory element should be either left or write. This allows a different interaction between neighboring bits within a memory element. Finally, the data pattern that originally is used can be different than what's defined in a walking 1s or 0s pattern For instance it can be random or something like 0x101. The 0x101 case shifting left would look like the following for DWords.