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CMOS Bleeder Disclosure Number: IPCOM000013840D
Original Publication Date: 2000-Nov-20
Included in the Prior Art Database: 2003-Jun-18

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The CMOS Bleeder For BiCMOS Circuit Disclosed is an implementation used in BiCMOS circuit intended to function as a bleeder to reduce the glitches. The implementation utilizes small CMOS pair to ensure the current flow in the complimentary side of the Differential Curent Switch (DCS) circuit. A typical DCS circuit is shown in Figure 1. A BiCMOS circuit, shown in Figure 2, has exactly the same function as the circuit in Figure 1, except the bottom inputs, BT and BC, can be rail-to-rail CMOS input voltages. This configuration may ensure that CMOS levels may not be translated to DCS input voltage levels. However, this implementation introduces glitches that are higher than that of DCS circuit. One way to reduce this induced glitch can be realized in the circuit shown in Figure 3. The implementation in Figure 3 functions as a bleeder. When current is flowing in one branch of the circuit, a weaker FET will conduct in the other branch and thus provide bleeder current. This ensures a bleeder current to reduce the glitch. A glitch in DCS poses more threat because DCS only has 200mV of noise margin. The other advantage of the implementation in Figure 3 is that it requires less area than conventional bipolar bleeder circuit. The conventional bipolar bleeder requires use of large resistor, which can be area consuming. A pair of weak FETs will take much less area than the large resistor.