Dismiss
The IQ application will be unavailable on Sunday, November 24th, starting at 9:00am ET while we make system improvements. Access will be restored as quickly as possible.
Browse Prior Art Database

Modular implementation for high-speed computer bus

IP.com Disclosure Number: IPCOM000013914D
Original Publication Date: 2000-Jan-01
Included in the Prior Art Database: 2003-Jun-19

Publishing Venue

IBM

Abstract

The primary embodiment consists of a series of modules into which memory devices (ie. DIMMs or RIMMS) can be inserted. The modules are designed to maintain the required impedance throughout. The only electrical connection to the bus controller is at the near end of the bus. Internal to the modules, the alternating signal and ground pins are arranged to create a series of controlled-impedance high-speed transmission line segments. The modules are designed to easily and flexibly connect physically together. This is useful for variable-length bus designs. Also disclosed is a physically-similar termination module that does not support memory devices but contains the appropriate signal termination circuitry for the bus. The modules may be designed to create a bus that is linear or one that turns in the third dimension. A combination of modules may be used for special applications. In an additional embodiment, the memory devices themselves are directly attached to the module (a RIMM or DIMM is not required). Although this would be a more expensive technology, it would have advantages in that possible discontinuities at the RIMM card edge connector are avoided.