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Method for Asynchronous Data Transfer between Chips Disclosure Number: IPCOM000013988D
Original Publication Date: 2000-Aug-01
Included in the Prior Art Database: 2003-Jun-19

Publishing Venue



Two chips are running at the same internal clock frequency, but their clocks are not aligned in phase. Data is transferred from one chip to the other at the full clock speed, without the need of an synchronization pattern. This disclosure describes a mechanism which allows the sampling of the incoming data with the receiving internal clocks, without the need of a training sequence or internal chip clock synchronization with PLLs. Also, the proposed mechanism allows for dynamic phase tracking in case of clock phase shifts, for instance due to temperature variations or change in clock distribution. How can one transfer data at the internal clock speed between two chips in speed expansion? Speed expansion is an expansion mode, by which multiple chips run in parallel in order to offer a higher port speed. This mode of operation requires transferring memory storage addresses from a master chip to one, or multiple, slave chips. In previous switch chips, solving this problem was not synchronous transfer of data could be achieved easily. With faster chip technology, the margins to achieve synchronous data transfer is by guaranteeing that both chips have their internal logic triggered at the same time.This requires the use of phase lock loops (PLL) in order to align clocks to a common reference. To avoid the burden of PLLs, one has to imagine either running the interface at lower speed (classic asynchronous interface) or using some kind of complex phase alignment mechanism, where typically a training pattern is used to chose one out of three (or more) clock phases for data sampling. The basic problem that has to be solved is to make a decision on a clock phase to sample the data such that none of the sampling latches are metastable. [Metastability occurs when the data being sampled by a latch changes value on the sampling clock edge. This leads to unpredictable data output, and oscillations. This state is resolved by double latching the data (two latches one after the other), such that no oscillation propagate into the rest of the logic. However, it is not possible to predict if the output will carry the new data value or the hold one on the next clock cycle].