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Prediction of I/O Sequential Data Access to Enable Enhanced System Performance

IP.com Disclosure Number: IPCOM000013995D
Original Publication Date: 2000-Oct-01
Included in the Prior Art Database: 2003-Jun-19

Publishing Venue

IBM

Abstract

Prediction of I/O Sequential Data Access to Enable Enhanced System Performance Disclosed is a method to enhance I/O performance, and therefore system performance, by performing a predictive fetch of the I/O translation information and data. In systems where 32-bit I/O devices must access 64-bit address spaces, it is necessary to have some sort of translation mechanism in the bridges to translate the 32-bit to 64-bit address. If this is not to be a fixed translation (which has many restrictions) then a dynamic method must be used, and such is the case in PowerPC platforms. In these systems a Translation Control Entry (TCE) is associated with each four kilobyte block of address space and this determines which I/O bus four kilobyte page will access which System Memory four kilobyte page. These TCEs are generally fetched when the devices first accesses a new page. The TCEs themselves are stored in system Memory, and there is a latency associated with the fetching of the TCE. This latency reduces I/O performance.