Browse Prior Art Database

Bidi Protocol to Block Store Operations for Minimum Fetch Latency

IP.com Disclosure Number: IPCOM000014037D
Original Publication Date: 2001-Nov-08
Included in the Prior Art Database: 2003-Jun-19

Publishing Venue

IBM

Abstract

The Problem: As more companies migrate toward e-commerce and world-wide trade, the dependency on high-performance, high-bandwidth computers is growing at a rapid pace. One of the measurements of quality of these computer systems is the performance. Because of the amount of data that gets transferred, it is important for these machines to keep up with the growing demand. One aspect of this growth is the ability for a Central Processing Unit (CPU) to obtain data as quickly as possible. This has led to larger L1 and L2 Cache sizes as well as larger storage to help support these CPs. Unfortunately, the packaging technology will usually not allow all these levels of cache to reside on one chip. This leads to two concurrent problems: 1. The delay involved in retrieving data from the next-level cache increases due to the packaging delay associated with a chip crossing, and