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Avoidance of deadlock for some PCI host bridges

IP.com Disclosure Number: IPCOM000014056D
Original Publication Date: 2001-Feb-01
Included in the Prior Art Database: 2003-Jun-19

Publishing Venue

IBM

Abstract

On the PCI system displayed below, multiple PCI Busses are connected together via PCI Host Bridges and PCI PCI Bridge Systems. The Host Processor can communicate with any of the PCI slot’s adapters on the Primary and Secondary PCI Busses. The PCI PCI Bridge Systems have connections to three PCI Busses; the Secondary PCI Bus, and two Primary PCI Busses. This PCI PCI Bridge System configuration allows any two adapters in the system to communicate with each other without using the Host Processor Bus, thus leaving the Host Processor Complex unaffected by the communication between the two adapters. This frees the Host Processor Bus for other operations. This configuration does present a problem with a possible deadlock condition when two adapters are communicating in opposite directions through the same PCI PCI Bridge System. For example, when an adapter in slot0 on PPCI-1 is communicating with an adapter in slot2 on PPCI-2 through PCI-PCI Bridge System 1. In this article, a solution to avoid this deadlock condition will be presented. S L