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A Method for Verifying the Correct Ordering of MMIOs and Invalidation Requests Across an IO Bridge

IP.com Disclosure Number: IPCOM000014068D
Original Publication Date: 2001-Sep-01
Included in the Prior Art Database: 2003-Jun-19

Publishing Venue

IBM

Abstract

A Method for Verifying the Correct Ordering of MMIOs and Invalidation Requests Across an IO Bridge Disclosed is an algorithm that efficiently verifies that processor storage accesses to IO devices (i.e. Memory mapped IOs or MMIOs) and processor invalidation requests to IO caches (i.e. Kill requests) are ordered correctly across an IO bridge. The algorithm uses a simulation of IO cache directories to quickly determine when it is required for a Kill request to propagate across an IO bridge, and then verifies that this Kill request is ordered the same way with MMIO requests on either side of the bridge. The algorithm is designed to work in a simulation environment that emulates hardware function via software simulation directly based on hardware specifications.