Browse Prior Art Database

Plating Head Design for Oxide Layer Removal Disclosure Number: IPCOM000014152D
Original Publication Date: 2002-Feb-15
Included in the Prior Art Database: 2003-Jun-19

Publishing Venue



Disclosed is a tooling method to allow for the oxide layer removal from a metal seed layer prior to plating, without later exposing the clean seed layer to atmosphere. The method is done completely in the plating cell. This method permits plating to begin instantly onto the pure metal seed. This method can be used to prepare the surface of any metal that forms a native oxide that is electrochemically soluble. In present plating system designs, whether they are cup or fountain plating, vertical or horizontal cell plating, paddle or laminar flow plating cell designs, all operations require some form of surface cleaning or treatment. That treatment takes various forms such as a plasma cleaning step or ash operation, or an acid pre-dip operation followed by a de-ionized water rinse. This design will allow for the removal of the oxide layer in the plating system and prevent the formation of any new oxide layer, allowing for a greater molecular bond between the seed and plated layers. With decreasing feature size, inter-layer adhesion is critical. Under computer control, once the wafer is placed into the plating bath, the anode and cathode connections of the power supply are switched so that the wafer becomes the anode and either a thief piece about the wafer becomes the cathode or an independent auxiliary cathode can be used. There is no electrical connection to the system anode at this time. The power supply is turned on in "reverse pulse" mode at a low level, removing the oxide layer from the wafer and depositing any contaminating material on the thief piece or auxiliary cathode. After a programmed time recipe step, the power supply shuts off, the anode connection is switched to the normal system anode and the plating power supply is turned back on in regular programmed plating mode: DC plating, pulse, or reverse pulse, as the process requires. An additional advantage of this method is that no material coming off the wafer is redeposited onto the anode, keeping it clean (Fig. 3). The figures below illustrate the normal power supply connections (Fig. 1) and the oxide removal connections (Fig. 2). Fig. 3 illustrates the electric field during the oxide layer removal electrical connections.