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Hardware Engine for Automatic DRAM ECC Scrubbing Disclosure Number: IPCOM000014209D
Original Publication Date: 2001-Jun-09
Included in the Prior Art Database: 2003-Jun-19

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As memory technologies have grown denser, the probability of single bits within the memory incorrectly changing state has increased significantly. Most ASIC chips with DRAM interfaces implement error correcting codes (ECC) that correct single bit errors and detect multibit errors. The correction that is done is in the data that is presented to the requester and not necessarily in the underlying memory. If multibit errors are detected, the subsystem is typically either reset or marked as failed at the system level. To decrease the probability that words within the DRAM memory that have single bit errors suffer a second bit flip resulting in an uncorrectable location, it is desirable to correct ("scrub") any single bit errors in the DRAM memory. Disclosed here is a hardware engine that automatically issues background reads to increment addresses in DRAM. When single bit errors are detected, the corrected data is written back to the memory location that had the single bit error. This method of scrubbing the memory of single bit errors has the following key advantages: 1) There is no firmware beyond hardware initialization required. 2) An access to a potentially failing location by the application is not required to scrub the location of an error. This prevents infrequently accessed locations from growing multibit errors