Browse Prior Art Database

DUTY CYCLE CHECKER FOR HIGH FREQUENCY SIGNALS

IP.com Disclosure Number: IPCOM000014212D
Original Publication Date: 2001-Apr-09
Included in the Prior Art Database: 2003-Jun-19

Publishing Venue

IBM

Abstract

DUTY CYCLE CHECKER FOR HIGH FREQUENCY SIGNALS In digital systems, some control signals such as reference clocks have a set of input requirements at Very Large Scale Integration circuit interface. One requirement is related to the ratio of the time at high state (or low state) with respect to the signal period, T0, also called Duty Cycle (DC). A common typical value is 50 with an allowed dispersion of a few percent. For high reliability operation , it is key to continuously check that this requirement is still met.