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CIRCUITRY AND METHOD FOR EVALUATING THE SPEED OF ASIC SEMICONDUCTOR DEVICE CIRCUITRY

IP.com Disclosure Number: IPCOM000014251D
Original Publication Date: 2000-Feb-01
Included in the Prior Art Database: 2003-Jun-19

Publishing Venue

IBM

Abstract

High Performance ASIC semiconductor devices are designed to operate within a predefined range of speed which is based on an ASIC's design and the speed of the components that comprise the ASIC device. Variations in ASIC fabrication both controlled and uncontrolled account for differences in speed of the components of one ASIC as compared to another ASIC having the same design and technology. These variations in speed may cause an ASIC to be rejected for use when it operates beyond the acceptable range of speed specified by the design, i.e., it operates either too fast or too slow. To assist manufacturing and/or development in identifying the speed of an ASIC, an ASIC may include performance circuitry and additional signal inputs/outputs (i/o's) which provide access to this circuitry. Given these, an ASIC's speed can be determined by contacting an external measuring device to these special i/o's. Disadvantages of this method are: Assignment of chip/die i/o's for performance measurement causes a reduction in the number of available signal i/o's to be used by the ASIC design. Product cost increases if a larger ASIC must be selected to accommodate required performance i/o's. Propagation of performance signal i/o's to "highest" level of package inflates cost of packages in addition to the ASIC. Performance monitoring i/o's may not be accessible post manufacturing assembly, making measurement impossible.