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Optimized algorithm for input bypass queue mechanism

IP.com Disclosure Number: IPCOM000014326D
Original Publication Date: 2002-Jan-20
Included in the Prior Art Database: 2003-Jun-19

Publishing Venue

IBM

Abstract

The Input Bypass Queuing mechanism described hereunder is composed of a FIFO memory which is used to enqueue and dequeue messages, a Write Pointer (WP) and a Read Pointer (RP). The memory width is N 1 where N is the number of bits of the messages. The additional bit called VALID_BIT is used to characterize the message in its memory position. VALID_BIT is written at ‘1’ during the write of the message written at ‘0’ when the message is processed (read)