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CIRCUIT TOPOLOGY TO MEASURE MR READ HEAD RESISTANCE AND CALIBRATE MR READ HEAD BIAS CURRENT

IP.com Disclosure Number: IPCOM000014344D
Original Publication Date: 2000-Aug-01
Included in the Prior Art Database: 2003-Jun-19

Publishing Venue

IBM

Abstract

The below described circuit topology will allow the measurement of the MR read head resistance and also the calibration of the MR read head bias current. The measurement of the read head bias resistance is important to make sure that the maximum power dissipation of the head is not exceeded The calibration of the bias current is important to allow operating closer to the maximum power dissipation by reducing the tolerance on the programmed bias current. Shown below is the block diagram of the circuit topology used for measuring the MR read head resistance and calibrating the head bias current. The main blocks in the diagram above and their purpose are: 7 bit current DAC for setting the current going to the on bias generator