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Technique to Speed-up Bitline Development Disclosure Number: IPCOM000014350D
Original Publication Date: 2001-Feb-01
Included in the Prior Art Database: 2003-Jun-19

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In designing arrays, the time to develop adequate signal on the bitline is crucial to meeting cycle time goals. During a read operation, one cell will pull the bitline from its precharged high state. Due to the load of the other cell hanging on the bitline, the pulldown rate is relatively slow. This technique helps to pull the bitline at a faster rate to reduce propagation delay. The technique is to connect a PFET to the bitline. The source of the PFET is connected to GND. The drain and the gate is connected to the bitline. When the bitline is being precharged, the bitline is high; therefore, the PFET is off. When the bitline is being pulled down (by a cell), the PFET turns on when the bitline has reached the thresh-hold voltage (Vt) of the PFET. Thus, the PFET helps to pull the bitline to GND at a faster rate. The PFET is only helping to pull the bitline to GND after the bitline has already been pulled to the Vt of the PFET and up to the bitline going to VDD-Vt, due to the body-effect (a PFET that has GND connected to its source will only pull the drain to Vt). For implementations that pull the bitline to rail, this technique will help significantly. For implementations that use a sense amplifier, the body of the PFET (in SOI) can be tied to GND to turn on the PFET at a lower Vt. Also, a low Vt version of the PFET can also allow the PFET device to help bitline signal development at an even lower Vt. 1