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Integrated, off-card implementation of high-speed memory bus Disclosure Number: IPCOM000014355D
Original Publication Date: 2000-Jan-01
Included in the Prior Art Database: 2003-Jun-19

Publishing Venue



The invention consists of a self-contained bus that is designed for easy physical connection to a host computer, printed circuit board. The self-contained bus is a linear, multiple conductor coaxial cable with specified characteristic impedance values that match the high speed bus requirement . The integrated bus uses an alternating signal and ground pattern for optimum transmission line properties, and it uses pins at the near end for easy insertion into a host computer, printed circuit board. At appropriate intervals along the cable, impedance-matched connectors are attached to the linear, multiple conductor coaxial cable. The far end of the integrated bus includes appropriate terminating components. As shown in the figure, the high speed bus is propagated to a plurality of impedance-matched connectors that are located off-board. A coaxial ribbon cable 1 forms the backbone of the integrated unit. The cable and connectors are designed to have a constant impedance throughout. A multitude of connectors 2 to which bus devices (such as RAMBUS memory modules) may be attached are located along the length of the coaxial ribbon cable. A termination block 3 is attached to the end of the cable to terminate all signals. 1 2