Browse Prior Art Database

Original Publication Date: 2000-Oct-29
Included in the Prior Art Database: 2003-Jun-19

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Background: An SMI (System Management Interrupt) is a high priority interrupt that is supported on current Intel and Intel-compatible microprocessors. An SMI event creates a unique context for the SMI handler to run in, regardless of the operational state of the microprocessor at the time of the SMI. SMM (System Management Memory) is required for supporting an SMI. At run-time SMM contains code, data, and save-state information (the context of the processor when the SMI occurs is saved in RAM). IBM products use the A000 and B000 segments (bank-switched memory that resides in the same area as VGA video memory, bank switched when an SMI occurs). Problem: The SMI handler in a typical PC (especially multiprocessor PCs) is getting larger than the A000 and B000 segments it typically resides in. As an example, features like USB Keyboard support (in BIOS) demands approximately 64K of RAM to operate. Solution: Use a section of memory at the top of system RAM. Reserve it (protect it) in all system service BIOS calls. Set up stack, code and data in the TOM (top of memory) area and use special macros and function calls to access data and make calls into the “Extended SMI Handler”. This mechanism provides a virtually unlimited space for an SMI handler. This mechanism can also be expanded to increase the amount of space available for POST. This implementation provides the added benefit that TOM memory is cacheable, thus enhancing the performance of the SMI handler. Example: (References Figure 1) Upon startup, POST determines the top of physical memory and reserves a portion of it for the Extended SMI Handler and adjusts all of the BIOS “memory size” calls accordingly. (This block of memory must be “hidden” from the operating system so application, kernel, and device driver code won’t be written on top of the Extended SMI area).