(PF/ASIC/DS) An efficient and comprehensive model to represent chip, package and system components that effect signal quality.
Original Publication Date: 2001-Dec-01
Included in the Prior Art Database: 2003-Jun-19
Customers of IBM ASICs use complex HSPICE models to simulate signals passing through both IBM and non-IBM made components. The models for the semiconductor circuits forming the logic functions and the I/O drivers are created by the library design team and made available to customers. The library offerings do not include models for the chip images and packages. This invention is a circuit model that can represent any chip size and package combination offered by IBM ASICs. Most of its implementation have been in HSPICE, but ASX versions have also been generated and other circuit modeling languages could be used as well. This invention provides an efficient model of the chip terrain and the package by the following means: 1. Utilizing the smallest repeatable subset of the chip topography to define the model area. In one particular implementation this refers to the area of the chip supplied by three ground, two Vdd and one Vdd2 c4 connections, approx. 1.2 sq.mm. For other chip images this may change, but it is expected to be a similarly small area. (Figure 1) 2. Identifying all the relevant features and activities contained in the model area using the assumption that the overall circuit activity is uniformly distributed on the chip surface. For example, if the overall chip area is 120sq.mm and the chip contains 600 I/O circuits, the 1.2sq.mm of model area would contain 6 I/O circuits (600x120/1.2). Similarly the model would contain 1/100 of all the clock buffers, latches, combinatorial logic circuits and arrays.