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IN-SITU STRESS CONTROL IN PLASMA PROCESSING

IP.com Disclosure Number: IPCOM000014385D
Original Publication Date: 2001-Apr-01
Included in the Prior Art Database: 2003-Jun-19

Publishing Venue

IBM

Abstract

A new technique for in-situ control of the stress profile during growth in plasma deposition and related environments, compatible with micro-electronic processing is described. This proposal relates to the use of various methods to deposit or etch thin layers of material as currently used in micro-electronics processing and related areas as well as control of the stress buildup during processing. In particular, for the new generations of the CMOS process thinner and thinner gate oxide layers are required with critical dimensions in the scale of several nanometers. Such gate insulators must be perfect without pin holes or defects and stress-free. Mostly such gate oxides are grown via LPCVD and this proposal might help to find a path for the use of PECVD tools. Another application is the plasma deposition of Si02 and similar nitride compounds for use as optical transparent layers (waveguides). In many cases the environments used to create such layers are extreme reactive, such as the plasma environment. Here it is difficult to use in-situ diagnostic techniques for process control. In particular the stress accumulated in thin films is a decisive factor in determining the performance and specifications of a thin film. The proposed method enables in-situ stress monitoring and feedback control during the growth of thin films.