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Level Sense Power On Reset Circuit Disclosure Number: IPCOM000014397D
Original Publication Date: 2000-May-01
Included in the Prior Art Database: 2003-Jun-19

Publishing Venue



Disclosed is a method to provide power on reset pulse of enough height even if rise speed of power supply is considerable slow. This circuit is implemented inside LSI chip and it resets internal memory devices such as latches, flip flops and registers and confirms initial state of those devices. As technology proceed on and on, power supply voltage is lowered for low power application. This makes it difficult to generate power on reset pulse with enough height. According to this method, the pulse height of the power on reset pulse is high enough by voltage sense mechanism with diodes. Figure 1 shows conventional power on reset circuit. This circuit has large capacitance C and resistance R to generate long charge up time. When the power is on, the capacitance C begins to be charged with path P through the resistance R. This charge up time should be long enough compared with the rise time of power supply in order to generate power on reset pulse of enough height. However the values of C and R are limited due to on-chip implementation. The maximum time constant CR which can be implemented on chip is about 1 msec even if ON resistance of MOSFET and poly-diffusion capacitance are used to implement R and C for area saving. The power supply rise time ranges from hundreds of micro-seconds to scores of milli-seconds. This causes low power on reset pulse and reset fail problem because the voltage of the power supply has not reached a enough voltage for resetting internal devices. Figure 2 shows the simulation result for the circuit. The height of the pulse is low when process is worst and rise speed of power supply is slow. 1