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CMOS Latch circuit Disclosure Number: IPCOM000014461D
Original Publication Date: 2002-Jan-01
Included in the Prior Art Database: 2003-Jun-19

Publishing Venue



This describes a new low power Scan latch circuit which improves its layout efficiency. Figure-1 shows an exsisting low power Scan Latch circuit. This circuit makes it possible to reduce capacitance of clock net because it uses only 2 NMOS for clock input instead of 2 NMOS and 2 PMOS of typical Scan Latch(Figure-2). In the low power Latch(Figure-1), 2 inverters which generate complemental signals of B and C clock are not used, either. As a result, power consumption can be reduced. On the other hand this circuit(Figure-1) consists of 7 PMOS and 19 NMOS. This unbalance, 7 PMOS vs 19 NMOS, increases its layout size because NMOS and PMOS are placed in pairs and the number of NMOS determins its layout size. Especially for Gate Array, inefficency is clear. Figure-3 shows the new schematic. It consists of 9 PMOS and 17 NMOS, total number of transistor is 26. Its layout size would be approximately 17/19=0.89 compared to Figure-1 circuit. One inverter is used to generate a complemental signal of A clock . But it would not be any concern for power consumption, because A clock is not used in functional mode. 1