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New Dry Etch-Back Process for Shallow Trench Isolation (STI)

IP.com Disclosure Number: IPCOM000014527D
Original Publication Date: 2000-Feb-01
Included in the Prior Art Database: 2003-Jun-19

Publishing Venue

IBM

Abstract

Disclosed is a dry etch process designed to improve the quality of the shallow trench isolation planarization used for advanced semiconductor products such as 16Mb DRAM chips. The shallow trench isolation consists of silicon oxide (SiO2) which fills the shallow trench recess in the silicon substrate. After the filling step, the structure is planarized in order to replicate a planar resist top surface down to shallow trench oxide surface. The conventional NF3/CHF3 chemistry has revealed a number of defects such as insufficient uniformity, wafer edge erosion, and low etch rate. A new O2/CF4/N2 chemistry is hereunder disclosed to overcome these drawbacks. The use of such a chemistry strongly improves etch rate (900nm/min) and wafer uniformity (non-uniformity is reduced from 1.8% down to 0.6%).