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Method for Determining SOI FET Floating Body Voltage Disclosure Number: IPCOM000014663D
Original Publication Date: 2001-Apr-26
Included in the Prior Art Database: 2003-Jun-20

Publishing Venue



Disclosed here is a circuit and method for determining the floating body voltage of the partially depleted silicon-on-insulator (PD/SOI) FET. Calibration of PD/SOI device characteristics is extremely difficult due to the complication of not knowing the exact voltage of a floating FET body. This difficulty adversely affects modeling accuracy. It often prevents the optimal use of the SOI technology due to timing uncertainties. Techniques indirectly measuring device parameters are currently utilized to determine the floating body voltage. These techniques include measurements of I-V curves, source/drain diode characteristics, and pulse/high-speed transient passgate leakage current measurements. This disclosure proposes a method to measure the SOI FET floating body potential, which embodies a concept of "monitoring without disturbing". This method uses a floating body charge monitoring technique, which does not require body contacts to the device under test (DUT). Therefore, intrinsic device behaviors are not altered or disturbed as a result of the presence of the body contacts. The body potential is determined iteratively by (1) comparison of voltage levels; and (2) cancellation of known voltage terms in the device model. In SOI product development, device and circuit designers can use this method to verify/calibrate the accuracy of circuit models for floating body devices. I. Variable Bias Charge Monitor Circuitry The biasing scheme of the floating body charge monitor technique [1-4] is generalized to register the SOI FET floating body voltage in a non-disruptive manner. The proposed recording element for the body voltage condition of the DUT is a variable bias charge monitor circuit as shown in Fig. 1a. In place of the Vdd rail implemented for the previously disclosed charge monitor circuits [1-3], bias voltages Vbiass (source bias of NFET1), Vbiasd (drain bias of NFET1), and Vbiasm (local high voltage rail for the current multiplier) are made variable to correspond to designated reference voltage levels and bias conditions. In this disclosure, the floating body charge monitor circuit is employed as a component for measuring body potentials, where an intentional bipolar current is generated in the monitor bias core upon circuit excitation, amplified by the current multiplier, and triggered/not triggered at the output of the latching element. Subsequently, the Triggered_state signal is used to determine the body potential status. Specifically, the charging voltage in the monitor core portion is made variable, instead of a fixed Vdd, to allow for intermediate voltage biasing, detection and calibration. Since the lower-than-Vdd operation stimulates less amount of parasitic bipolar current, a two-stage current multiplier serves to amplify the current and sensitize the latching element under acceptable noise margin requirements. For the purpose of simplicity and illustration, a basic current mirror-style circuit is used for the current multiplier. More sophisticated current multiplier can be used if needed. Since the magnitude of observed current is very critical in design, the bodies of PFET3, PFET4, NFET3, and NFET4 are connected through body contacts to Vdd and ground, respectively. This is to guarantee identical switching characteristics for auxiliary circuitry when two or multiple such monitors are employed for comparison. 1