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Method and Apparatus for the Placement of Signals Onto Lanes of a Byte Lane Selectable Bus to Provide Maximum Flexibility in Selecting Signal Groups

IP.com Disclosure Number: IPCOM000014687D
Original Publication Date: 2001-Jun-10
Included in the Prior Art Database: 2003-Jun-20

Publishing Venue

IBM

Abstract

Method and Apparatus for the Placement of Signals Onto Lanes of a Byte Lane Selectable Bus to Provide Maximum Flexibility in Selecting Signal Groups The use of a programmable, byte lane selectable bus requires that the placement of the various processor units/signals be assigned to byte lanes/bit positions of the bus so that required signal groups can be observed concurrently. The method of this disclosure is an interative process which produces a solution accommodating the maximum number of required groups within the constraints of the byte lane selectable bus design. The method for optimizing signal placement on the bus considers the constraints of the byte lane selectable bus, the signal groups required for analysis, and the signal placement necessary to support that analysis. The method involves several steps which generally are described as chosing activities to be anaylzed, identifying the signals needed for the analysis, forming groups of signals for the analysis areas, arranging units across the bus input muxes to support the groups, placing groups of signals onto the mux byte lanes for each unit, and assigning each signal in a byte lane to a specific bit position. The details of these steps are now presented together with the tools and techniques developed for the method of this disclosure.