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ESD Protection Design for Gate Line Leed on TFT/LCD Disclosure Number: IPCOM000014692D
Original Publication Date: 2000-Jan-01
Included in the Prior Art Database: 2003-Jun-20

Publishing Venue



Disclosed herein is a ESD (electrostatic discharge) protection for gate line lead on TFT/LCD, where dummy metal line close to the last gate line and increasing plane metal area connected to the counter electrode (ITO) through transfer pad. For large size and thin glass TFT/LCD, electrostatic charge in process (TFT fabrication and cell fabrication) is easier to occur and causes breakdown to metal even through passivation layer. For TFT design, Cs (storage capacitor) line-connections and V com line connections are put on gate line edge side close to separated metal lead for TAB (tape automated bonding) connection. Usually transfer pad is designed on space between gate-metal lead separation. In case of this, the electrostatic discharge is easily occurred to closest gate-line lead from charged space for transfer pad area. By this ESD, the worm-bite shape appeared on the edge of gate-line lead, and causes line defect or line discontinuity for the worst case. To protect discharge damage to the actual gate line lead, two protection method are described, which are: minimizing electrostatic charge by transfer pad design and specially designed dummy-metal line lead to be discharged intentionally. Figure shows TAB design to protect ESD failure, where includes dummy metal line (next to and covering Cs lead line), and large plane-shape (home-base shape in this case) common electrode (V com) pad. The key point is double protection as: 1) intentional ESD occurrence to the restricted or expected position by dummy metal line, 2) minimization of electrostatic charge by larger common electrode (V com) or transfer pad area The dummy metal is designed for intentional ESD occurrence of electrostatic charge stored on the glass surface. By this design, ESD to Cs line or V com pad is protected. The dummy metal line is put next to and covering the Cs lead lines and/or V com lead line as shown. The ESD pin design is also effective to restrict the position of ESD occurrence. The common electrode (V com) pad is designed to be larger like home-base shape, in order to increase the same electrical-potential area with the counter electrode (ITO) on CF (color filter) after transfer applied. This consideration is very important to protect ESD after cell assembly. The dummy metal line is not restricted next to Cs lead line and/or V com lead line, and the modified dummy is possible such as not straight line, not surrounding home-base shape V com pad. The common electrode (V com) pad is not restricted as home-base shape as shown, as stripe shape for mark drawing, and other modification will be fine.