Method for System On Chip timing analysis
Original Publication Date: 2001-Apr-22
Included in the Prior Art Database: 2003-Jun-20
System On Chip (SOC) refers to large chips which include several functional units such as a processor core and memory subsystem which in the past would have resided in separate chips. One consequence of these large chips is that they have a lot of timing paths. Timing paths are measurements of how long it takes an electrical signal to travel from the start of an electronic circuit, until it reaches the end of the circuit. The start of a timing path can be a storage element such as a latch. The data output of this latch usually connected to a series of electronic circuits and the result of this circuit is usually captured by another storage element such as a latch. This is where the timing path usually ends. It is important that these timing paths arrive at a certain time so that the capture latch can sample the result of the circuit. This is the main reason that a chip can run at certain clock frequency. During chip development, every possible timing path is measured and reported using a "Static Timing" tool such as Einstimer or Pathmill. These tools will print a report, which by nature of SOC, is very large. The job of the design engineer is to look through the report and fix timing paths by changing the circuit that does not meet clock frequency.