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A method for scan based memory test to supplement built-in self-test

IP.com Disclosure Number: IPCOM000014759D
Original Publication Date: 2000-Nov-01
Included in the Prior Art Database: 2003-Jun-20

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Disclosed is a method for scan based memory test to supplement built-in self-test. The problem was to detect certain processor chip array defects that could not be detected using existing test methods. The existing method for testing the arrays is to run a series of test patterns to all locations and check for errors. This is accomplished using special hardware within the chip called array built in self test (ABIST). The ABIST controller is designed to test all location of all arrays with certain data patterns and in a set order. The patterns and order are predetermined to be the best for finding all defects in the arrays. To find these defects, we invented a method using scanning that controlled the ABIST controller and allowed us to run test patterns using a new data pattern and access order. By doing this, we used the power of the ABIST controller to load and execute a unique pattern to all arrays in parallel and check all the arrays in parallel (thus increasing the speed significantly over scanning directly to the arrays). This method was very successful in detecting this unique defect and allowed us to weed out the bad chips. This method allows array test patterns to be added after a chip is fabricated, without re-RITing the design. Thereby allowing good chips to be sorted from bad ones.