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IP.com Disclosure Number: IPCOM000014782D
Original Publication Date: 2000-Oct-18
Included in the Prior Art Database: 2003-Jun-20

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Problem This invention disclosure proposes a solution to the problem of testing and rapidly diagnosing AC scan chain defects and localizing these defects to a failing Shift Register Latch (SRL) or associated scan clock tree. This on-the-fly quick and accurate pinpointing of systematic and random circuit faults can be performed during the test process of most scan based designs. The concept can be further enhanced and extended to diagnose similar AC defects encountered in BIST structures incorporating On-Product Clock Generation (OPCG) support. These type of problems are usually encountered early in the technology's life cycle and their diagnosability is critical in improving the process so it quickly achieves manufacturing yield levels. An inability to improve the technology and yield of the device can greatly impact a program or at least severely minimize the revenue that could be realized. Rapid diagnosis to a location for Physical Failure Analysis (PFA) is needed to understand and correct the process anomalies. Figures and Drawings