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Method and apparatus for implementing byte serial semantics in a register-based instruction set architecture Disclosure Number: IPCOM000014793D
Original Publication Date: 2000-Mar-01
Included in the Prior Art Database: 2003-Jun-20

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Byte serial semantics are required for the correct implementation of storage-to-storage oper- ations in System/390. This poses several problems in the execution using binary translation to a register-oriented architecture since a high-performance implementation will use "widening" to perform operations not at the byte level, but at the machine word level. The present disclosure describes a hardware solution to ensure byte-serial semantics while allowing widening to be used for efficiency. A difference between byte-serial and word-based processing can only be observed in the case of overlapping source and target operands. (sup 1) Thus, widening can still be used beneficially in the majority of cases, and special care must be taken to detect overlap of operands which need special processing. The approach described herein is based on using address buffers associated with some or all registers in the architecture to detect overlap between the source and target address of a storage-to-storage operation. Since storage-to-storage operations are two-operand instructions, the target address is also present as one source operand. This observation is used to further simplify address overlap checks to an address overlap check between the two source operands. When a System/390 storage-to-storage operation is translated to a sequence of register oper- ations, a special load instruction deposits the memory addresses into the address buffers of the associated registers. A later ALU operation then examines the contents of these address regis- ters executes the operation in byte serial semantics (or raises an exception and transfers control to a software handler which emulates the byte serial semantics in software).