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Emulating Multi-Way Set-Associativity Through an Address Mapping Scheme Disclosure Number: IPCOM000014799D
Original Publication Date: 2001-Jun-14
Included in the Prior Art Database: 2003-Jun-20

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Introduction A 2-way set-associative cache of size N/2 has about the same miss rate as a direct-mapped cache of size N (Hennessy and Patterson: Computer Architecture, A Quantitative Approach). However, a 2-way set associative cache involves more complex logic and a larger hit time compared to a direct-mapped cache. The technique described herein seeks to achieve a similar miss rate reduction as a 2-way or multi-way set-associative cache compared to a direct-mapped cache, at a much smaller increase in complexity and hit time. Reduction of the cache miss rate results in a smaller number of memory accesses experiencing the relatively large miss penalty of an access to main memory and can substantially improve overall computer performance.