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Pass Gate Filtering Technique In CMOS Dynamic Logic Circuit

IP.com Disclosure Number: IPCOM000014816D
Original Publication Date: 1999-Nov-01
Included in the Prior Art Database: 2003-Jun-20

Publishing Venue

IBM

Related People

Authors:
Jeff Tran

Abstract

Disclosed is a design and method for using pass gate to reduce or to eliminate unwanted input noise signals in CMOS dynamic logic circuit. As technology continues to improve, the structure of the MOSFET becomes smaller. Scaling down the MOSFET increases the driving capability of the device, and enhance the performance of the IC. However, the MOSFET is very susceptible to noise because of its lower operating threshold voltage(Vt). Such a problem poses major challenges in dynamic circuit design because unintentional input signals(noise) may turn on the MOSFET device, and causes the circuit to function improbably. Figure 1. A Typical 2-way AND-OR CMOS Dynamic Circuit Figure 1 shows a typical 2-way AND-OR dynamic circuit. An unintentional noise signal can be driven on any of the inputs A, B, C, and/or D. Such a problem happens would caused FET devices 101, 102, 104 and/or 105 to turn on prematurely and discharged the node PRE; it would potentially tripping the output node OUT to the wrong state. A larger size of the feedback half-latch device 103, or a smaller output inverter 106 can be used to keep the circuit functionally controlled. However, such techniques degrade the performance of the circuit.