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A method to efficiently analyze the Area Array on chip C4 power distribution by defining the smallest representative partition based on the (gnd,vdd,vddx) repeatable C4 power distribution pattern

IP.com Disclosure Number: IPCOM000014823D
Original Publication Date: 2001-Dec-01
Included in the Prior Art Database: 2003-Jun-20

Publishing Venue



This invention enables the analysis of Area Array on chip C4 power distribution to be defined in a small repeatable window. Since this window is uniformly repeated over the entire chip, the electrical analysis done within the window can be applied to the entire chip due to symmetry. This greatly reduces the amount of work and size of data that one has to analyze for electrical characteristics (e.g. electromigartion, IR drop and di/dt). Without applying the idea of this invention, a large area or the entire chip C4 power distribution will have to be analyzed and therefore takes much longer and utilize much more resources. The C4 distribution of an Area Array image for gnd, vdd and vddx forms a pattern that is repeated over the entire chip. The pattern and the ratio of gnd and power pins may be different for different technologies but a particular pattern can always be identified in an Area Array image due to it's uniform distribution. 1. First, observe the layout of gnd, vdd and vddx C4s and define the smallest possible "C4 window" that captures two properties of the image. The first property is the ratio of gnd, vdd and vddx within this window is the same as the ratio of the entire chip (e.g. 3 gnds to 1.5 vdd, 1.5 vdd2). Second, this "C4 window" can be repeated in all directions by just moving it to the next adjacent window area in all 4 directions (up, down left and right). However, an even smaller subset of the "C4 window" may be defined if the "C4 window" can be constructed by mirroring the "subset window" and the subset window has the same gnd, vdd and vddx ratio (first property). 2. Analyze the electrical characteristic of the "subset window" and apply the result to the "C4 window" with adjustment of mirror image. Then, the result of the "C4 window" can be applied throughout the chip due to its identical distribution. Examples of analyses that can be done are current through C4 for electromigration concern, power bus resistance from C4 and noise generated in this window due to I/O circuit di/dt. Below is an example of the smallest "C4 window" and "subset window" identified for an Area Array image: